1. Field of the Invention
This disclosure relates to a photo mask set and a semiconductor device fabricated using the same and, more particularly, to a photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same.
2. Description of Related Art
As semiconductor devices become more highly integrated, a multi-layered interconnection technique has been widely used in fabrication of the semiconductor devices. The multi-layered interconnection technique includes forming lower interconnection lines on a semiconductor substrate, forming an interlayer insulating layer on an entire surface of the substrate having lower interconnection lines, and forming upper interconnection lines on the interlayer insulating layer.
Meanwhile, the lower interconnection lines or the upper interconnection lines are typically formed by sequentially forming a conductive layer and a photoresist layer, forming a photoresist pattern using a photolithography technique with a photo mask, and etching the conductive layer using the photoresist pattern as an etching mask.
The photo mask includes a transparent substrate and opaque layer patterns formed on the transparent substrate. The width of the opaque layer patterns and the spaces therebetween should be reduced in order to realize the highly integrated semiconductor devices. In this case, a proximity effect easily occurs during the photolithography process. The proximity effect may cause degradation of the resolution limit. Therefore, various photo masks and diverse fabrication methods of the photo masks have been proposed in order to suppress the proximity effect.
Photo masks for reducing the proximity effect are taught in U.S. Pat. No. 5,242,770 by Chen, et al. entitled “MASK FOR PHOTOLITHOGRAPHY”, which is incorporated herein by reference.
FIG. 1A and FIG. 1B are plan diagrams illustrating a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines, respectively, and the first and second photo masks are described in the U.S. Pat. No. 5,242,770. FIG. 1C is a is a plan diagram illustrating the first photo mask and the second photo mask aligned with the first photo mask.
Referring to FIG. 1A, a first lower opaque pattern 20a, a second lower opaque pattern 20b, and a third lower opaque pattern 20c are positioned parallel to each other on a first transparent substrate 1. The second lower opaque pattern 20b is interposed between the first and third lower opaque patterns 20a and 20c. In addition, the first and third lower opaque patterns 20a and 20c extend past the end of the second lower opaque pattern 20b. 
Furthermore, intensity-leveling bars (not shown) are located in appropriate positions in order to reduce the proximity effect. The intensity-leveling bars do not have large sizes (e.g., wide widths), which are sufficient to generate photo resist patterns on a semiconductor substrate during the photolithography process.
Referring to FIG. 1B, a first upper opaque pattern 40a, a second upper opaque pattern 40b, and a third upper opaque pattern 40c are positioned parallel to each other on a second transparent substrate 3. The first to third upper opaque patterns 40a, 40b, and 40c are positioned to overlap with the first to third lower opaque patterns 20a, 20b, and 20c, respectively. Other intensity-leveling bars (not shown) may be disposed on the second transparent substrate 3.
Referring to FIG. 1C, the first to third lower opaque patterns 20a, 20b, and 20c are overlaid with the first to third upper opaque patterns 40a, 40b, and 40c, respectively. While the width of the lower opaque patterns is greater than that of the upper opaque patterns, the second upper opaque pattern 40b extends lengthwise past an end of the second lower opaque pattern 20b. 
FIG. 2A is a plan diagram useful for explaining multi-layered interconnection lines fabricated using the first and second photo masks illustrated in FIGS. 1A and 1B.
Referring to FIG. 2A, lower interconnection lines 20a′, 20b′, and 20c′, corresponding to the lower opaque patterns 20a, 20b, and 20c, respectively, are formed on a semiconductor substrate. Also, upper interconnection lines 40a′, 40b′, and 40c′, corresponding to the upper opaque patterns 40a, 40b, and 40c, respectively, are formed over the semiconductor substrate.
In this case, a defect region 40b″ may be formed at a portion of the second upper interconnection line 40b′ that crosses over the end of the second lower interconnection line 20b′. 
FIGS. 2B, 2E, and 2F are cross sectional diagrams useful for explaining a method of forming multi-layered interconnection lines using the conventional photo masks shown in FIGS. 1A and 1B. In each of the drawings, a region indicated by a reference character “A” corresponds to a cross sectional diagram taken along a line I-I of FIG. 2A, and a region indicated by a reference character “B” corresponds to a cross sectional diagram taken along a line II-II of FIG. 2A.
Referring to FIG. 2B, a first lower interconnection line to a third lower interconnection line 20a′, 20b′, and 20c′, which are parallel to each other, are formed on a semiconductor substrate 10 using the first photo mask. An interlayer insulating layer 30 is formed on the substrate having the lower interconnection lines 20a′, 20b′, and 20c′. The interlayer insulating layer 30 may have a surface step difference as shown in FIG. 2B, even though the interlayer insulating layer 30 is planarized. In the drawing of FIG. 2B, a step distance SD is defined as the shortest horizontal distance from the end of the second lower interconnection line 20b′ to the point where the interlayer insulting layer 30 has the lowest surface level with respect to the second lower interconnection line 20b′. 
An upper conductive layer 40 is formed on the interlayer insulating layer 30. The upper conductive layer 40 has the same surface profile as the interlayer insulating layer 30.
A photoresist layer 50 is coated on the upper conductive layer 40. The photoresist layer 50 is then exposed to a light L1 that passes through the second photo mask. As a result, the photoresist layer 50 is defined to have a first pattern region P1, a second pattern region P2, and a third pattern region P3 corresponding to the first to third upper opaque patterns 40a, 40b, and 40c of FIG. 1B and an exposure region E between the first to third pattern regions P1, P2, and P3. Unfortunately, a portion of the second pattern region P2 underneath the second upper opaque region 40b may be exposed during the exposure process. This is due to a light L2, which is the portion of the light L1 that is irregularly reflected off a sloped surface of the upper conductive layer 40 between the extensions of the first and third lower interconnection lines 20a′ and 20c′. This irregular reflection may occur even though the second photo mask employs intensity leveling bars to reduce the proximity effect.
FIG. 2C and FIG. 2D are plan diagrams illustrating the sloped surfaces of the upper conductive layer 40 and a direction of the reflected light L2.
Referring to FIG. 2C, contour lines {circle around (1)} to {circle around (8)} represent points of equal height on the surfaces of the upper conductive layer 40 of the semiconductor substrate. As the number increases from {circle around (1)} to {circle around (8)}, the surface of the upper conductive layer 40 becomes lower. Accordingly, there are not only sloped surfaces parallel with the x-axis or the y-axis but also sloped surfaces Sxy directed to axes between the x-axis and the y-axis that are formed near the end of the second lower interconnection line 20b′. 
Referring to FIG. 2D, the photoresist layer 50 (shown in FIG. 2B) is coated on the upper conductive layer 40. The photoresist layer 50 is then exposed by the light L1 that passes through the second photo mask, as described with reference to FIG. 2B. As a result, the photo resist layer 50 is defined to have the first pattern region to the third pattern region P1, P2, and P3 corresponding to the first to third upper opaque patterns 40a, 40b, and 40c of FIG. 1B and the exposure region E between the first to third pattern regions P1, P2, and P3. However, a portion of the second pattern region P2 can be exposed during the exposure process. This is due to the light L2, which is irregularly reflected off the sloped surface of the upper conductive layer 40.
In particular, a light L2xy is reflected off the sloped surfaces Sxy, the surfaces Sxy directed to axes between the x-axis and the y-axis, and a part of the light L2x that is parallel to the x-axis is focused on a focus area F1 in the second pattern region P2. A focus distance FD is defined as the distance between the end of the lower interconnection line 20b′ and a center of the focus area F1, a minimum focus distance SFD as a shortest distance between the end of the second lower interconnection line 20b′ and the focus area F1, and a maximum focus distance LFD as a longest distance between the end of the lower interconnection line 20b′ and the focus area F1.
Referring to FIG. 2E, the photoresist layer exposed by the light L1 is developed using a developer. As a result, the first to third photoresist patterns P1, P2, and P3 corresponding to the first to third pattern regions P1, P2, and P3 are formed on the upper conductive layer 40. Also, a thin narrow abnormal region P2′ is formed at the focus area F1 in the second photoresist pattern P2 because the photoresist layer at the focus area F1 is exposed by the reflected light L2x and L2xy. 
Referring to FIG. 2F, the conductive layer 40 is etched using the first to third photoresist patterns P1, P2, and P3 as etching masks. As a result, the first to third upper interconnection lines 40a′, 40b′, and 40c′ corresponding to the first to third photoresist patterns P1, P2, and P3 are formed. In this case, the second upper interconnection line 40b′ includes a defect region 40b″ at the focus area F1. This is due to the abnormal region P2′ in the second photoresist pattern P2. As a result of this serious flaw, the second upper interconnection line 40b′ may be disconnected at the defect region 40b″. 
As described above, in the case of forming multi-layered interconnection lines, the sloped surface of the upper conductive layer caused by forming the under interconnection lines results in poor photoresist patterns and poor upper interconnection lines, even though a photo mask reducing the proximity effect is used.
Embodiments of the invention address these and other disadvantages of the prior art.